1. Field of the Invention
The present invention relates to an exposure method and a method for manufacturing a semiconductor device.
2. Description of the Related Art
To increase the integration degree of semiconductor integrated circuit devices, it is important to form patterns at a high density. Thus, for example, a NAND flash memory has been proposed which has contact holes for bit line contact displaced from one another (see, for example, Japanese Patent No. 3441140). FIG. 21 is a diagram showing mask patterns used to form the contact holes. As shown in the figure, openings (light transmission portions) used to form the contact holes are displaced from one another.
However, the above opening patterns are dense in an oblique direction, reducing the sizes of process windows indicating exposure latitude (EL) and the depth of focus (DOF). This makes it difficult to inhibit possible dimensional errors during an exposure step. Consequently, it has been difficult to form accurate patterns with possible dimensional errors inhibited.